tag:blogger.com,1999:blog-3652428531631827883.post2209145614432430375..comments2024-03-28T09:46:09.997+01:00Comments on The New Citavia Blog: AMD's Zen core (family 17h) to have ten pipelines per coreDresdenboyhttp://www.blogger.com/profile/15574049389666017448noreply@blogger.comBlogger15125tag:blogger.com,1999:blog-3652428531631827883.post-9036460495006406272022-02-06T05:38:40.066+01:002022-02-06T05:38:40.066+01:00Love this blog!!!Thanks a lot for sharing this wit...Love this blog!!!Thanks a lot for sharing this with all folks you actually read my mind Definitely believe that what you said. Thanks for sharing this marvelous post. I m very pleased to read this article. You have touched some pleasant factors here. Any way keep up wrinting. Feel free to visit my website; <a href="https://www.betmantoto.pro/" title="토토" rel="nofollow">토토</a> <br /><br />oncasinosite 카지노사이트https://www.blogger.com/profile/07784016991982993287noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-42009105053365661882015-11-29T21:26:20.598+01:002015-11-29T21:26:20.598+01:00I see, thx! Hopefully it's going to become com...I see, thx! Hopefully it's going to become competitive again like in the good ole' days :)Anonymoushttps://www.blogger.com/profile/11173826432761622471noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-13369178795706366802015-11-14T12:08:02.184+01:002015-11-14T12:08:02.184+01:00Daniela, it's the result of finishing a postin...Daniela, it's the result of finishing a posting and a diagram at 3 a.m. But that statement should fit, as about 95% of the diagram represents, what is shown in the patch or patents, it still fits I think. I leaved out the L1 I$ size (none given) and borrowed one idea from Jaguar. So small changes might be necessary, but the important elements are backed by the available leaks/sources.Dresdenboyhttps://www.blogger.com/profile/15574049389666017448noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-21195861150810216032015-10-28T22:22:04.256+01:002015-10-28T22:22:04.256+01:00In English "with little speculation" mea...In English "with little speculation" means you're pretty sure - is that what you'd meant or "a little speculation" is still warranted? Anonymoushttps://www.blogger.com/profile/11173826432761622471noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-67677504573801931192015-10-06T08:43:30.333+02:002015-10-06T08:43:30.333+02:00I'm trying to compare Haswell load/store units...I'm trying to compare Haswell load/store units with Zen l/s units. Haswell has 256bit l/s units, while Zen is probably going to have 128bit l/s units. What I don't quite understand is that Zen has dedicated l/s units + some l/s capabilities in fp units, while haswell only has ports specifically for l/s operations. Does this mean that Haswell units can load whatever they want while Zen has two dedicated l/s units for integer ops and l/s capabilities inside fp pipes for fp ops. Is this correct?<br /><br />Another thing I'm not sure about is that according diagram found here:<br /><br />http://www.anandtech.com/show/6355/intels-haswell-architecture/8<br /><br />Haswell has units that l/s data and units that l/s adress. I imagine those units are different?? There is no load data unit on this diagram. How is that possible?<br /><br />I'm sorry if those are noob questions, I'm not very knowledgeable about processor design.<br />Anonymoushttps://www.blogger.com/profile/08506505475852339615noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-56135628320453645942015-10-05T22:47:25.592+02:002015-10-05T22:47:25.592+02:00sky scraper, this table by yuri shows, to which th...sky scraper, this table by yuri shows, to which the load or store related fp ops go. In earlier AMD processors (K8, K10 I think), each of the three FP units could execute a load, while the cache could only provide two 64bit values. This was only done to simplify or equalize the design of these units, and maybe also to reduce blocking.<br />Dresdenboyhttps://www.blogger.com/profile/15574049389666017448noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-28725094031235774882015-10-05T21:37:48.018+02:002015-10-05T21:37:48.018+02:00According to this: http://pastie.org/private/xrq95...According to this: http://pastie.org/private/xrq95cijhfhrlmpeyngrq there are load and store capabilities present in fpu pipes. Can they be utilized also for integer load/store or are they strictly for fp load/store?Anonymoushttps://www.blogger.com/profile/08506505475852339615noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-46054902236163936472015-10-04T22:34:18.418+02:002015-10-04T22:34:18.418+02:00The Haswell diagram http://www.anandtech.com/show/...The Haswell diagram http://www.anandtech.com/show/6355/intels-haswell-architecture/8 gives a much better overview of what-goes-where questions.Jan Ziak (atomsymbol)https://www.blogger.com/profile/00398184141815003668noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-14602880884686211992015-10-04T17:19:01.727+02:002015-10-04T17:19:01.727+02:00The FPU units seem to be 128 bit wide because many...The FPU units seem to be 128 bit wide because many common SSE and 128 bit AVX instructions are of type fast-path decode (one uop) while equivalent 256 bit AVX ops are double decode (going to 2 pipelines or maybe even to one but sequentially).<br /><br />And one FMAC grouping is not 256 bit wide but does the 128 bit FMUL first, accompanied by the FADD unit for the final result. So these 2 "FMACs" are 128 bit wide too. And if there is no copy-paste error in the patch, the FPU might even just start one FMAC and not two during one cycle, as the 2 options for a FMUL are always paired with the FADD in fp pipline #3.<br /><br />I'll write a follow up soon.Dresdenboyhttps://www.blogger.com/profile/15574049389666017448noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-23104628006783600692015-10-04T06:05:50.280+02:002015-10-04T06:05:50.280+02:00I asked for a SOURCE for this claim of FPU's b...I asked for a SOURCE for this claim of FPU's being 128-bit wide. Not to repeat it again. Repeating anything without a source does not make it any more true.<br />Heikkihttps://www.blogger.com/profile/17832739911276147059noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-89600787982890499152015-10-04T00:39:18.191+02:002015-10-04T00:39:18.191+02:00There are two 128 bits floating point add units an...There are two 128 bits floating point add units and two 128bits floating point multiply units. 256bits operands in 128high and 128low Lo Absolutohttps://www.blogger.com/profile/15008068214703421186noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-68339304205493685632015-10-03T21:10:18.117+02:002015-10-03T21:10:18.117+02:00Oh, didn't notice that, but yes, can't fin...Oh, didn't notice that, but yes, can't find it among the real 2015 slides I have either, true.<br /><br />ClausDKhttps://www.blogger.com/profile/17316022248136309279noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-88040247007242748582015-10-03T19:48:03.882+02:002015-10-03T19:48:03.882+02:00Those may 2015 slides are fakesThose may 2015 slides are fakesHeikkihttps://www.blogger.com/profile/17832739911276147059noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-30796120922358291912015-10-03T19:06:28.280+02:002015-10-03T19:06:28.280+02:00AMDs own Zen slide (may 2015) shows 2x256bit and 6...AMDs own Zen slide (may 2015) shows 2x256bit and 6 integer-units. Lots of speculations ;)ClausDKhttps://www.blogger.com/profile/17316022248136309279noreply@blogger.comtag:blogger.com,1999:blog-3652428531631827883.post-43576339902118161972015-10-03T16:45:13.802+02:002015-10-03T16:45:13.802+02:00Is there any actual source which states/hints that...Is there any actual source which states/hints that the FPU's are (only) 128 bit wide?Heikkihttps://www.blogger.com/profile/17832739911276147059noreply@blogger.com