Monday, February 1, 2016

AMD Zeppelin CPU codename confirmed by patch and perhaps 32 cores per socket for Zen based MPUs, too

The Zeppelin codename, first mentioned on a leaked slide shown by Fudzilla, has been identified as a "family 17h model 00h" CPU by a patch on The interesting parts of the patch are:
AMD Zeppelin (Family 17h, Model 00h) introduces an instructionsretired performance counter which indicated byCPUID.8000_0008H:EBX[1]. And dedicated Instructions Retired register(MSR 0xC000_000E9) increments on once for every instruction retired.

There might even be a meaning behind the similarity of parts of the "Zen" and "Zeppelin" codenames.

An older patch on the same mailing list also gives a little more info about Zen:

On AMD Fam17h systems, the last level cache is not resident in Northbridge. Therefore, we cannot assign cpu_llc_id to same value as Node ID (as we have been doing currently)
We should rather look at the ApicID bits of the core to provide us the last level cache ID info. Doing that here.
The most interesting part describes the way, how the last level cache (LLC) ID is being calculated for Zen based MPUs:

+ core_complex_id = (apicid & ((1 << c->x86_coreid_bits) - 1)) >> 3;
+ per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;

"Core complex" should be similar to "compute unit" and has been used in some AMD patents already. The expression marked in red means a shift right by 3, which equals a division by 8. So with two logical cores per physical core due to SMT, a core complex should contain four Zen cores and a shared LLC.

The next line shows the socket ID being shifted left by 3, leaving 3 bits for the core complex ID, which suggests a maximum number of eight core complexes per socket, or 32 physical cores. This number should first be seen as a placeholder, but we've already seen rumours mentioning that many cores.

1 comment:

Smile Like You Mean It said...

It appears that CERN has confirmed that Zeppelin will offer up to 32 cores and 8 DDR4 channels.

I don't know if the speaker at this presentation is correct, but he states that AMD will be using MCM packaging to put 32 cores in a single socket. This implys that the Zeppelin die is a 16 core design with 4 DDR4 channels.

Breaking this down into the core complexes you've described that would give us 4 per die for a total of 8.

Extrapolating from there to Summit Ridge we should be looking at an 8 core chip using two core complexes and offering 2 DDR4 channels in line with the rest of the AM4 platform. This also means that Summit Ridge will use a different die than AMD's Zeppelin.

Again this all assume that Zeppelin is a 2 die MCM. It could alternatively be constructed using four Summit Ridge dies to put 32 cores and 8 DDR4 channels in a single socket.